Trends in the semiconductor industry indicate a growing importance for devices of the complementary insulated gate field effect transistor (Complementary IGFET or CMOS) type. As used in integrated circuits, complementary IGFET devices, in turn, are decreasing in size and increasing in density. To successfully manufacture these devices requires a process which is easily manufacturable, provides adequate isolation between devices, and provides acceptably low leakage within each device.
Isolation between devices is achieved by providing a thick field oxide with a suitably doped region aligned beneath the thick oxide. The doped region is usually formed by ion implantation and must have a concentration of dopant which is carefully controlled to provide an acceptably high field threshold voltage without reducing the breakdown voltage of the junction formed between the doped region and an adjacent source or drain region to a value below the value of operating voltages used within the circuit.
As the size of the devices used in an integrated circuit are reduced further and further, the so called "short channel" effects begin to become important. As the channel length decreases, for a given operating voltage, punch through caused by the spread of the drain depletion region into the channel region becomes significant. Some protection against punch through is afforded by a subsurface increase, for example by ion implantation, in the doping of the device substrate beneath the channel region. The punch through protection implant is of the same doping type as the field enhancement implant, but is typically of a different magnitude and a different location within the device.
In addition to meeting electrical specifications, the integrated circuit must be commercially manufacturable. The ability to successfully manufacture an integrated circuit is enhanced by reducing the number of masking layers required to implement the process and by reducing the criticality of alignment of each masking layer. A process for fabricating a complementary IGFET circuit which will have the required physical and electrical characteristics and which will be useful in a manufacturing environment, therefore, requires steps for implementing doped field regions and, where needed, punch through protection. These must be implemented with a minimum of additional masking steps and with a minimum of critical masking steps.
It is therefore an object of this invention to provide an improved process for fabricating a complementary insulated gate field effect transistor circuit.
It is another object of this invention to provide an improved process for fabricating complementary IGFET devices having complementary doped field regions.
It is still another object of this invention to provide an improved process for fabricating semiconductor devices including doped field regions and punch through protection.
It is yet a further object of this invention to provide an improved process for fabricating semiconductor devices including non-compensating doped field regions with optional punch through protection.